1. Field of the Invention
The invention relates to a performance evaluation system and method for evaluating the effective number of bits and the differential non-linearity of an analog-digital converter (ADC) which converts an analog signal into a digital signal and which is implemented by a single semiconductor integrated circuit or a combination of a plurality of semiconductor integrated circuits.
2. Description of the Related Art
An approach to evaluate ADC's is categorized into a static and a dynamic characteristic evaluation technique. According to the static characteristic evaluation technique, a precisely defined d.c. voltage is applied to an ADC, which is a device under test (DUT), and a response from the ADC is observed in order to estimate "a difference between the transition voltage of an actual ADC and the transition voltage of an ideal ADC" in a computer or like means based on the differential nonlinearity, hereafter referred to as DNL. The differential nonlinearity or DNL is obtained by the comparison of a difference in the upper limit amplitude of the analog signal (actual step size) as adjacent quantized codes are delivered from the ADC against an ideal step size which corresponds to 1 LSB, and enables a localized fault which depends on a particular code to be detected. Thus, DNL for ADC is defined as follows: EQU DNL=A.sub.in (Q.sub.m+1)--A.sub.in (Q.sub.m)-1[LSB] (1)
where Q.sub.m+1 and Q.sub.m are two adjacent quantized codes and A.sub.in (Q.sub.n) represents the upper limit of the amplitude of the analog signal which corresponds to a quantized code Q.sub.n. It is seen that DNL equals zero if "the difference between adjacent transition amplitudes" remains constant and equals the step size corresponding to 1 LSB. However, the static characteristic evaluation technique cannot determine the nonlinearity of an ADC under test which depends on the frequency of a signal being applied.
On the other hand, according to the dynamic characteristic evaluation technique, a periodic signal is applied to an ADC under test, a response from the ADC is observed, and "a difference between the transitional voltage of an actual ADC and the transition voltage of an ideal ADC" is; estimated as in a computer. This technique has an advantage that a characteristic which closely approximates an actual operation of the ADC, which is under test, can be estimated. Dynamic characteristic evaluation techniques which utilize a sine wave (sinusoidal wave) as an input signal include a histogram approach, an FFT approach and a curve fitting approach mentioned below.
(a) In the histogram approach, a sine wave signal from a sine wave generator 11 is applied to an ADC 14 under test, as shown in FIG. 1A. Using a digital waveform which represents the response of the ADC, a histogram for respective codes is obtained by a histogram analyzer 17. A DNL estimator 18 then determines a difference between the histogram for the actual ADC and the histogram of an ideal ADC, and divided by the histogram of the ideal ADC, thus estimating the DNL. The normalization of the difference in the histograms by the histogram of the ideal ADC accounts for a non-uniform distribution of the sine wave histogram. By way of example, the relative number of samples for an output from a 6 bits ADC will be as shown in FIG. 1B where the total number of samples is equal to 1024, and the resulting DNL will be obtained as shown in FIG. 1C.
(b) In the FFT approach, a digital signal representing the response of the ADC 14 under test is Fourier transformed as by FFT (fast Fourier transform), and is separated in the frequency domain into a signal (namely, a frequency spectrum of the sine wave applied) and noises (namely, a spectrum of quantization noises or a sum of spectra other than the frequency of the sine wave applied), thus determining a signal-to-noise ratio (SNR).
Specifically, as shown in FIG. 2A, a sine wave signal from a sine wave generator 11 is passed through a low pass filter 12 to eliminate unwanted components therefrom before it is fed to a sample-and-hold circuit 13 where the sine wave signal is sampled periodically and held therein for feeding an ADC 14 under test. A response output from the ADC 14 is fed to an FFT unit 15 where it is transformed into a signal in the frequency domain, which is then fed to an SNR estimator 16. On the basis of a result of the FFT as illustrated in FIG. 2B, the SNR estimator 16 determines the signal-to-noise ratio SNR by dividing the sine wave signal component G.sub.SS (f.sub.0) by the noise component .SIGMA..sub.f G.sub.nn (f) where f.noteq.f.sub.0.
If the quantization noise increases in the ADC 14 for reason of fault, the signal-to-noise ratio SNR is degraded, increasing the number of bits among the total number of bits in the ADC 14 which are influenced by the quantization noise. It is then possible to estimate the effective number of bits (ENOB) of the tested ADC from the signal-to-noise ratio observed, and can be given by the equation (2) indicated below. ##EQU1##
By changing the frequency f.sub.0 of the sine wave signal applied, the frequency dependency of ENOB can be determined.
(c) In the curve fitting approach with the sine wave, parameters (such as frequency, phase, amplitude, offset etc.) of an ideal sine wave are chosen so that the square error between a sampled digital signal and the ideal sine wave is minimized. An rms (root-mean-square) error determined in this manner is compared against the rms error of the ideal ADC having the same number of bits to estimate the effective number of bits.
Means for generating an analog signal such as a sine wave is described in detail in "Theory and Application of Digital signal Processing" by Lawrence R. Rabiner and Bernard Gold; Prentice-Hall, 1975, in particular, "9.12: Hardware realization of a Digital Frequency Synthe-sizer", for example.
Problems with the use of conventional dynamic evaluation approach are discussed below.
(a) When the histogram approach is used to estimate the DNL of an ADC with a high precision, a very long time is needed for the determination. By way of example, an estimation of the DNL for an 8-bit ADC with a reliability of 99% and for an interval width of 0.01 bit requires 268,000 samples. For a 12-bit ADC, as many as 4,200,000 samples are required. (See, for example, Joey Doernberg, Hae-Seung Lee, David A. Hodges, 1984.) When the ADC under test exhibits a hysteresis, it is likely that any fault therein cannot be detected by using the histogram approach. Here it is assumed that when an input signal crosses a given level with a positive gradient, a corresponding code breadth is enlarged, increasing the number of observations, while when the input signal crosses the given level with a negative gradient, the corresponding code breadth shrinks, decreasing the number of observations. According to the histogram approach, no distinction is made in the direction in which the input signal changes, and accordingly, the number of observations for the positive gradient and the number of observations for the negative gradient are added together in the ultimate number of observations. Hence, an increase and a decrease in the number of observations cancel each other, and the code breadth will be one close to a code breadth for a fault-free ideal ADC. (See, for example, Ray K. Ushani, 1991.) As a consequence, the DNL which can be estimated with the histogram approach is a result of comparison of a difference in mean values of output code breadth against the ideal step size corresponding to 1 LSB. In addition, there must be a relationship other than an integral multiple between the frequency of the input sine wave and the sampling frequency of the ADC. (See, Joey Doernberg, Hae-Seung Lee, David A. Hodges 1984.)
With a histogram approach using the sine wave input, the estimated value of DNL remains little unchanged if the internal noise of the ADC is high or low. In other words, there remains a problem with a histogram approach that the influence of the internal noise of the AE)C upon the performance of the ADC cannot be exactly estimated (Ginetti, 1991). Accordingly, the histogram approach cannot be applied for the evaluation of the performance of multi-bit ADC with a high accuracy.
(b) Problems involved with the FFT approch to estimate the effective number of bits will now be described. To enable an accurate observation of the noise spectrum from the ADC under test using the FTT approach, it is necessary that the standard deviation ##EQU2##
be made sufficiently small. (See, J. S. Bendat and A. G. Piersol, 1986.) The number of samples N must be increased at this end. When the number of samples is increased by a factor of 4, the noise level will be 6 dB lower. The computation of FFT requires a number of real number multiplications, which is indicated below ##EQU3##
and a number of real number additions, which is indicated below ##EQU4##
The ADC converts an analog signal into a digital output code in accordance with the amplitude of the input signal. If the Fourier transform of the output signal is used in evaluating the conversion characteristic of ADC, non-idealities which are localized in individual output codes cannot be separated. This is because defects present within different codes are added together as noises to the rms error. Thus if there is no correlation between the defects and if different codes are influenced by them, these defects will be evaluated as "part of noises which coherently influence the same code." As a consequence, there is a likelihood that the effective number of effective bits may be underestimated. (See, Robert E. Leonard Jr.) At the same time, an analysis of individual factors which cause a reduction in the effective number of bits such as DNL, integral nonlinearity (INL), aperture jitter or noise is prohibited. Thus, the effective number of bits which can be estimated by this approach is not an instantaneous value which corresponds to each output code, but is a mean value determined over the entire output codes. Moreover, there is a need to provide a relationship other than an integral multiple between the frequency of the input sine wave and the sampling frequency of the ADC in order to randomize the quantization error. (See, Plassche, 1994.)
(c) Finally, a problem with the curve fitting approach will be considered. With this approach, it is necessary to estimate the parameter of the ideal sine wave by the method of least squares. (1) To estimate the frequency of the ideal sine wave, the Fourier transform takes place only for a single presumed frequency to determine the power. When the power reaches a local maximum, the frequency is estimated. The local maximum cannot be found unless the frequency estimation is repeated at least three times. Thus, this requires 9N (where N represents the number of samples) real number multiplications and (6N-3) real number additions. (2) The estimation of the phase requires 2N real number multiplications, (2N-2) real number additions, one real number division and one calculation of arctangent. (3) The estimation of the amplitude requires 2N real number multiplications, (2N-2) real number additions and one real number division.
Where the operation of the ADC under test largely departs from its normal operation or where the digital waveform from the ADC under test. contains a reduced number of samples, the square error does not approach a given value if the calculation of the square error is repeated while changing the parameter of the sine wave. Thus, the error diverges rather than converges. To give an example, since the variance of the frequency estimate is proportional to 1/N.sup.3, a sufficiently great number of samples, in excess of 4096 samples, are necessary to suppress the variance. The effective number of bits which can be estimated by this approach corresponds again to a mean value determined over the entire output codes. As a consequence, an analysis of individual factors such as harmonic distortion, noise or aperture jitter which causes a reduction in the effective number of bits is prohibited. In addition, there must be a relationship other than an integral multiple between the frequency of the input sine wave and the sampling frequency of the ADC. If the sampling frequency were an integral multiple of the frequency of the input sine wave, the input signal would be coherent to the sampling, with consequence that only a specific quantization level would be tested. (See, the paper by Ray K. Ushani.)
Problems with the prior art technique for evaluation of dynamic characteristics of the ADC can be summarized as follows: The histogram approach determines a probability density function by an approximation of a mean value of the histogram of the input sine wave. Accordingly, the DNL or the effective number of bits estimated according to any technique represents a mean value rather than an instantaneous value. As a consequence, it is difficult to estimate independently factors of a compounded fault. In the process of estimating the effective number of bits for an ADC which uses a sine wave as an input signal, a relationship other than an integral multiple must be established between the frequency of th(e input sine wave and the sampling frequency of the ADC. For this reason, an arbitrary frequency cannot be selected as the testing frequency. In addition, a very increased number of samples are required for any technique chosen. Assuming a number of samples equal to 512, the volume of computation needed is as follows:
FFT approach: 4092 real number multiplications and 7668 real number additions; PA1 curve fitting approach: 6656 real number multiplications and 4092 real number additions. PA1 FFT approach: 4092 real number multiplications and PA1 curve fitting approach: 6656 real number multiplications and PA1 instantaneous amplitude calculation means: PA1 digital moving differentiator means: PA1 Daubechies wavelet transform means:
It is a first object of the invention to provide a system for and a method of evaluating an AD converter which is capable Of estimating an instantaneous effective number of bits and an instantaneous differential non-linearity and which is capable of independently dealing with factors of a compounded fault.
It is a second object of the invention to provide a system for and a method of evaluating an effective number of bits and a differential non-linearity of an ADC which permits an arbitrary choice of a testing frequency.
It is a third object of the invention to provide a s y stem for and a method of evaluating an effective number of bits and a differential non-linearity of an AD converter which can be implemented in a simple hardware.
It is a fourth object of the invention to provide a system for and a method of evaluating an AD converter which is capable of estimating an effective number of bits or a differential non-linearity with a high accuracy of determination, without increasing the length of testing time.
It is a fifth object of the invention to provide a system for and a method of evaluating an AD converter which permits the observation of an instantaneous effective number of bits and a differential non-linearity as a function of time.